Vehd

library ieee;  - - type memoria is array (2**M-1 downto 0) of std_logic_vector (N-1 downto 0);
use ieee.std_logic_1164.all; -- signal mem : memoria;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
entity alu_tb is
end alu_tb;
architecture sim of alu_tb is -- constant tclk : time := 10ns;
component alu -- clk_i<=not clk:i after tclk/2;
generic ( -- hacer clk asimetrico clk_i<='1' after 25 ns when clk_i = '0' else '0' after 75 ns;
N : positive);
port (
a, b : in std_logic_vector (4*N-1 downto 0);
opr : in std_logic;
ovfw_sign : out std_logic;
resultado : out std_logic_vector (4*N-1 downto 0));
end component;
constant N : positive := 4;
signal a_i, b_i : std_logic_vector (4*N-1 downto 0);
signal opr_i : std_logic;
signal ovfw_sign_i : std_logic;
signal resultado_i : std_logic_vector (4*N-1 downto 0);
begin -- sim
DUT: alu
generic map (
N => N)
port map (
a => a_i,
b => b_i,
opr => opr_i,
ovfw_sign => ovfw_sign_i,
resultado => resultado_i);
Tecnología Electrónica. ITI-EI FebExt 2009
10/10
process
file arch : text ;
file res : text open write_mode is "resultado.txt";
variable buf, buf2 : line;
variable dat2 : std_logic_vector(4*N-1 downto 0);
variable v1 : std_logic;

begin
file_open(arch,"datos.txt", read_mode) ;
opr_i<='0';
while not endfile(arch) loop
readline (arch, buf);
hread (buf, dat2);
a_i <= dat2;
hwrite(buf2, dat2);
write (buf2, string'( " + " ));
hread (buf, dat2);
b_i <= dat2;
hwrite(buf2, dat2);
write (buf2, string'( " = " ));
wait for 10 ns;
v1:=ovfw_sign_i;
write(buf2, v1);
dat2 := resultado_i;
hwrite(buf2, dat2);
writeline(res, buf2);
end loop;
file_close(arch);
write(buf2, character'(' '));
writeline(res, buf2);
file_open(arch,"datos.txt", read_mode) ;
opr_i<='1';
while not endfile(arch) loop
readline (arch, buf);
hread (buf, dat2);
a_i <= dat2;
hwrite(buf2, dat2);
write (buf2, string'( " - "));
hread (buf, dat2);
b_i <= dat2;
hwrite(buf2, dat2);
write (buf2, string'( " = "));
wait for 10 ns;
v1:=ovfw_sign_i;
if v1='1' then
write(buf2, character'('-'));
else
write(buf2, character'(' '));
end if;
dat2 := resultado_i;
hwrite(buf2, dat2);
writeline(res, buf2);
end loop;
file_close(arch);
file_close(res);
assert false report "fin simulación" severity failure;
end process;
end sim;